1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of forming electrodes on a substrate.
2. Description of the Related Art
Semiconductor devices with a three-dimensional structure comprising stacked semiconductor substrates are known. In such devices, integrated circuits formed on the upper surfaces of different substrates or ‘chips’ are interconnected by conductive (e.g., copper) electrodes that pass through one of the substrates, or by a series of such electrodes passing through a series of substrates. The electrodes, sometimes referred to as through-chip via electrodes, are first formed in holes that pass only partway through each substrate from its upper toward its lower surface. After electrode formation, the lower substrate surface is etched away until the lower ends of the electrodes are exposed.
Japanese Patent Application Publication (JP) No. 2001-345324 discloses a method of forming such electrodes that begins by forming holes in the substrate by a dry etching process such as reactive ion etching (RIE). Next an insulating film and a layer of barrier metal are deposited on the surface of the substrate, including the interior sides and bottom surfaces of the holes. The barrier metal layer has two functions: to prevent diffusion of the electrode material into the substrate and to ensure tight contact of the electrode material with the interior of the hole. To obtain these two effects, a plurality of barrier metal layers may be formed one on another as disclosed in, for example, JP 11-345933.
After the barrier layer or layers have been formed, the holes are filled with the copper or another electrode material by an electroplating process. This process deposits electrode material not only in the holes but also on the entire surface of the substrate. The electrode material and barrier metal outside the holes are then removed, usually by chemical-mechanical polishing (CMP), leaving the electrodes in the holes.
Since CMP is a time-consuming process with a low polishing rate, JP 2001-345324 teaches the removal of material deposited outside the holes by an etching process followed by CMP. The etching process quickly removes most of the electrode material from the surface of the substrate. The barrier metal layer is used as an etch stopper: etching stops when this layer is exposed. Due to surface irregularities, some of the electrode material deposited on the barrier metal outside the holes is also left, so that the exposed surface is a patchwork of barrier metal and electrode material. The CMP process then removes the electrode material and barrier metal from parts of the substrate surface outside the holes.
CMP, which is also widely used to planarize layers and films, employs a polishing pad and a chemical slurry. A problem is that the slurry is expensive and is consumed in large quantities. The method of JP 2001-345324, which uses CMP to remove the barrier metal and part of the electrode material from areas outside the holes, is therefore costly. It would be desirable to have a less expensive method of removing the unwanted electrode material and barrier metal.